Are the FIFO's accessible (for either reads or writes) when the part enters BIST mode (CY7C924ADX or CY7C9689A) | Cypress Semiconductor
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Are the FIFO's accessible (for either reads or writes) when the part enters BIST mode (CY7C924ADX or CY7C9689A)
1)Can I read characters from the RXFIFO during BIST mode (CY7C924ADX or CY7C9689A)?
2)Can I write characters to the TXFIFO during BIST mode (CY7C924ADX or CY7C9689A)?
Receive FIFO: (When RXBISTEN* is enabled and RXFIFO is enabled) All writes to the RXFIFO are SUSPENDED. Any data present in the RXFIFO will also remain in the FIFO and cannot be read until BIST operation is complete. RXFULL* flag will be used to present BIST progress until BIST is disabled. The RXFIFO will be bypassed, but the data present in the FIFO will remain valid. RXFULL* is used to signify the beginning of each BIST loop.
Transmit FIFO: (When TXBISTEN* is enabled and TXFIFO is enabled) All reads from TXFIFO are SUSPENDED and BIST generator is enabled. The TXFIFO remains available for loading of data. It may be written up to its normal maximum limit while BIST operation takes place. TXEMPTY* flag will be used to present BIST loop status until BIST is disabled. On the TX side, it is NOT bypassed. You can still load data to the TXFIFO while BIST is running.
This behavior is documented in more detail starting on pg. 39 of the datasheet.
200-MBaud HOTLink Transceiver (Attached Below 38-02008_0D_V)
TAXI-compatible HOTLink Transceiver (Attached Below 38-02020_0C_V)