Advantage of multiple stop bits at Transmitter side for all PSoC devices | Cypress Semiconductor
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Advantage of multiple stop bits at Transmitter side for all PSoC devices
What is the recommended number of stop bits for UART transmitter?
If you are using UART for communication, it is always advantageous to use multiple stop bits at the transmitter side than at the receiver side. Assume that your PSoC is configured as receiver. Let the transmitter is configured to have more than one stop bits. When the stop bits from the transmitter reaches the receiver, even if the receiver misses one of the stop bits, it will be possible to detect another stop bit. Also the time slots allotted for the extra stop bits creates a time delay which can be used effectively for buffering data or for some other purposes at the receiver side. So using more than one stop bits at the transmitter side is advantageous.
In PSoC1 UART Transmitter, stop bit can only be 1 whereas in PSoC 3/5 stop bit can be 1/1.5/2 bits