Address Valid Time When Using AUTOPTR1/2 for External Data Memory Access | Cypress Semiconductor
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Address Valid Time When Using AUTOPTR1/2 for External Data Memory Access
When the FX2/FX2LP 8051 runs the code above, the address valid time is only for 2 CLK cycles: different from what is stated on page 39 of the datasheet. The MOVX @DPTR, A and MOVX A, @DPTR with DPTR pointing to one of the autopointers have a data cycle with the target address only valid for 2 FX2 Clocks.
The external 8051 bus does not agree with the timing diagram outlined in sections 9.3 and 9.4 of the datasheet.
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 will only be active while either RD# or WR# are active. The address of AUTOPTR2 will be active throughout the cycle and meet the address valid time which is based on the stretch value. Scetion 9.3 and 9.4 of the latest version of the datasheet provides this information.