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Address pin numbering in QDR II SRAMs

Last Updated: April 18, 2012

Why are the address lines not numbered in the pin out section of the QDR II datasheet?


The memory array of the QDR II device is arranged differently than standard Sync/ NoBL SRAMs. If you choose a QDR II 2 word burst SRAM, then the memory is split into 2 different memory blocks and every read is fetched from 2 different blocks. If you choose a 4 word burst SRAM,then the data fetched during a read operation is fetched from 4 separate memory blocks. The QDR device does not have an internal burst counter (unlike standard Sync/ NoBL SRAMs) and hence there will not be any A0 and A1 pins. The address pin numbering does not matter as long as you do not remove the connections to the device after you perform a write operation. Thus there is no need for any numbering of the pins A0, A1, A2 etc.

Please refer to this KB article - and AN4025 Application note for more information on Std. Sync, NoBL SRAMs.
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