ADC gives incorrect value when CapSense is enabled | Cypress Semiconductor
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ADC gives incorrect value when CapSense is enabled
When input to an ADC is taken from a MUX bus and if CapSense is enabled, the ADC produces incorrect results? What is the reason for this error and how can this be corrected?
While the CapSense is running, the precharge clocks will continuously charge and discharge the Cmod capacitor connected at Analog Mux Bus. Thus, the voltage across Cmod will create an offset for the input signal connected on analog mux bus. The signal which ADC see at its input will be the sum of input signal and the voltage across Cmod. Thus, it'll give the wrong values.
1. Stop the CapSense UM before measuring the analog signal using ADC.
2. Disconnect the Cmod from the bus. The below mentioned code snippet can be used for enabling and disabling the external connected capacitor.
backup_amux = AMUXCFG;
AMUXCFG &= 0xC0; // Disable external cap
backup_clock = OSC_CR1; // Take the backup of VC1 and VC2 divider as it determines the resolution and scan speed of CSD
OSC_CR1 = 0x66; // Load the VC1 and VC2 divider with the desired column clock divider values
After completing the ADC measurement, restore AMUXCFG and OSC_CR1:
AMUXCFG = backup_amux;
OSC_CR1 = backup_clock;