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Active Analog Filter Application Using PSoC® 4 - KBA87492

Last Updated: May 27, 2016

How do I build an active analog filter using PSoC 4’s analog resources? 


Most of the PSoC 4 devices have more than two opamps that can be used to build the analog front-end of a system. This knowledge base article shows an example of a single-pole lowpass filter. If you are new to PSoC 4, see AN79953, Getting Started with PSoC® 4. If you are new to PSoC Creator, see the PSoC Creator home page.

The Top Design of the filter is shown in the following diagram. 

Top Design of the filter

In the Top Design, components and connections marked in blue are external to the device. 

Two opamps are used in this design: one for the active low-pass filter and the other to buffer the bias voltage. 

Because opamps in PSoC 4 operate with a single supply, if the input signal is expected to go negative relative to the VSS of the PSoC device, you must clamp it to a fixed voltage so that the negative voltage does not appear at any PSoC pin. In this design, the input signal is clamped to the bias voltage of VDD/2, which is generated using a potential divider formed by external resistors R4 and R5. This voltage is buffered by Opamp_BIAS, which is then added to the input signal using the C2-R3 network.

Note that C2 and R3 form a high-pass filter for the input signal. You should set the cut-off frequency of this network based on the application requirements. With the values shown in the Top Design, the network provides an attenuation greater than 3 dB for frequencies less than 0.72 Hz. 

Opamp_LPF forms the single-pole low-pass filter. The external resistors R1 and R2 set the passband gain as shown in the following equation: 

Passband gain = 1 + R1R2

Resistor R1 and capacitor C1 set the cut-off frequency as indicated in the following equation:

Cut off frequency (Hz)12 * Π * R1 * C1

With the values mentioned in the Top Design, the passband gain comes as 11 and the cut-off frequency as 1.592 kHz. Note that the output will be clamped to the bias voltage of VDD/2. 

You can use the PSoC Creator project KBA87492 with the default device set to CY8C4247AZI-M485, provided with this article. Open the project, change the device if you are using a different device, build it, and verify the analog resources consumed in the device on the “Analog” tab of the .cydwr file. It is shown in the following screenshot for reference (CY8C4247AZI-M485). OA1 forms the buffer for the bias voltage and OA0 forms the filter.



Note: Use PSoC Creator 3.3 CP1 or later versions for this project.

File TitleLanguageFile SizeLast Updated
Download 212Hz_LPF.cydsn.zipEnglish168.43 KB07/10/13
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