Achieving a Local Transfer Rate of 96MB/s in FX2 | Cypress Semiconductor
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Achieving a Local Transfer Rate of 96MB/s in FX2
How can the local transfer rate of 96 MB/s be achieved?
The burst rate of 96MB/s can be achieved by running the Slave FIFOs at 48 MHz (internal or external clock), while asserting SLWR or SLRD/SLOE for the entire data burst phase. Assuming active low polarity signals, when writing to the Slave FIFOs, SLWR should be held low as each word is clocked on the rising edge of IFCLK. The case is similar for reading from the Slave FIFOs; SLOE/SLRD should be held low as each new word is read on every rising edge of IFCLK.
The technical reference manual assumes a conservative approach as the examples show a word being clocked on every other IFCLK edge. This is for systems that may not be able to abide by the setup and hold times required for a burst phase like what's described above. Clocking a word on every other edge would then reduce the effective burst rate to 48 MB/s.
1) FX2 has the ability to have the FIFO flags assert one word prior to the FIFO becoming full, and one word prior to the FIFO becoming empty. This give the external master additional time to check the FIFO status flags.
2) To achieve the 96MBs, the control signals will have to be active while each word is clocked on the rising edge of IFCLK.
3) The endpoints and FIFOs share the same physical memory space. Often you'll see them referred to as "endpoint FIFOs" because they exhibit a dual personality. There are basically two domains the endpoint FIFOs reside in, the USB domain, and the peripheral interface domain. FX2 is able to switch clock domains to pass the packet pointers from one domain to the other, thus seemingly able to "connect" the USB domain to the peripheral interface domain. This is how it maximizes the USB 2.0 bandwidth without need of processor intervention. Sometimes it's easier to think of the FIFO space in terms of buffers, consistent with the different buffering schemes the FX2 can take on. The possible buffering schemes are shown on page 14 of the datasheet. Only EP2 and EP6 can be configured for the larger 1024 FIFO size.
4) The FIFO full and empty flags are packet based and therefore represent packet boundaries. For example, if the EP6 full flag is not asserted (active low, and assuming EP6 is configured for 512-byte size, 2x buffered), then there is at least room for one more packet (512 bytes) in the FIFO. Conversely, if the EP2 empty flag is not asserted (active low, and assuming EP2 is configured for 512-byte size, 2x buffered), then there is at least one more data packet to be read by the external master (512 bytes).