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Custom programmer for CY7C63803 | Cypress Semiconductor

Custom programmer for CY7C63803

Summary: 1 Reply, Latest post by Madhu Sudhan on 25 Jun 2016 06:05 AM PDT
Verified Answers: 0
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benwolsieffer_1668361's picture
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I am attempting to create a custom programmer for a CY7C63803 chip. I have the programming spec, and it seems fairly easy to understand (but perhaps it could go into a bit more detail), but I have been completely unable to get the device to communicate with the programmer. I was wondering if there was anyone on these forums who has experience with the protocol for programming this chip (the protocol is significantly different from the standard ISSP protocol used on most PSoC 1 chips).

My programmer currently sends the READ-PROGRAM-REG mnemonic and read the response, but the target never appears to drive STKDATA, which simply floats once the programmer finishes sending.

Oddly, the spec defines Tvddwait as "VDD stable to Wait-And-Poll hold off", which seems to imply that the programmer should Wait-And-Poll directly after power on, but this is never mentioned anywhere else in the spec. On the other hand, this procedure is how the standard PSoC 1 ISSP protocol initializes communication, so I though I might try it. When I sent the 20 STMCLK cycles required to start Wait-And-Poll, the target did appear to respond, but not in any way defined by the spec.

My experience so far has left me very confused, and I was wondering if anyone had any insight.

mady's picture
Cypress Employee
963 posts


Please create a Tech Support case with us, as we need to analyze your requirements in detail.


-Madhu Sudhan

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