A weird question about FLAG | Cypress Semiconductor
A weird question about FLAG
I have modified the SyncSlaveFifo sample to achieve four auto channel among PC,FX3 and FPGA, they are:
channel 0 is PC --->FPGA, thread 0, FLAGA is configured to DMA_THREAD0_READY ,polarity is low
channel 1 is PC --->FPGA, thread 1, FLAGB is configured to DMA_THREAD1_READY ,polarity is low
channel 2 is FPGA --->PC, thread 2, FLAGC is configured to DMA_THREAD2_READY ,polarity is low
channel 3 is FPGA --->PC, thread 3, FLAGD is configured to DMA_THREAD3_READY ,polarity is low
data from channel 0 will loopback to channel 2, so do channel 1 and 3, I call channel 0 and 2 the PairA, 1 and 3 are PairB
Now I'm doing the stress test , when PC pours packets within 2k bytes(more or less) into channel 0, FPGA can loopback these packets to PC through channel 2, so do the PairB.
the question is, when PC pours packets into PairA and PairB simultaneously, the PairA works well but PairsB is blocked, whether I pour PairA first or PairB, it's strange.
FPGA tells me when PairB is blocked, the FLAGD is always low, which means the buffer is full, so FPGA can not write in any packets.
The two weird things: one is the problem always happend on PairB, not PairA, though they have the same config; the other is PairB works well when I test it independently.
If my english or description is poor, I‘m sorry