USB 3.0 Channel Analysis with Cadence Allegro (SigXplorer) | Cypress Semiconductor
USB 3.0 Channel Analysis with Cadence Allegro (SigXplorer)
I try to design a PCB for FX3. For verification I use SigXplorer in Allegro. I have some problem in simulating USB 3.0 (SSTX-/+ & SSRX-/+) by SigXplorer.
in 5 Gbps my eye diagram of USB 3.0 channel will be corrupt. I import directly USB 3.0 Driver & Reciever from IBIS model in SigXplorer then add 90 ohm diffrentional channel with 0.1 ns delay. but I get bad result in simulation on 5 Gbps. Also I try it with 50 ohm termination resistor at the end of every track , but my result isn't correct.
there is anybody have experience in this subject for help me?