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Suffer from partial full abnormal behavior | Cypress Semiconductor

Suffer from partial full abnormal behavior

Summary: 1 Reply, Latest post by PRAG on 02 Jan 2015 02:52 AM PST
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Broccoli's picture
4 posts



I am using 16 bits SlaveFIFO on FX3, PCLK is operate at 100MHz


sending data from FPGA via FX3 to PC


FLAGA is setted as current_thread_full


FLAGB is setted as current_thread_partial_full (as shown in Figure1)


While I monitor FLAGA only, data losses during transmittion. Currently, FLAGB operates normally.


After searching the comments on Forum.


I "ANDed" FLAGA and FLAGB inside FPGA then monitor this signal. But something strange happened...


FLAGB always keep low, no matter how many times I ask data from FX3


Do you guys have any experience or comment on it??

PRAG's picture
Cypress Employee
173 posts


What is the configuration of the watermark flag for the thread/socket you are accessing?

AND'ing the two signals may not be enough. You need to consider the polarities and what exactly the signals imply.

Config of partial/watermark flag is done in firmware through the CyU3PGpifSocketConfigure() API.

You would use the full_flag to determine whether there is a buffer available to write to.

And you would use the partial_flag to determine when to stop writing to the buffer (to determine the end of buffer / buffer boundary).

If you know the exact number of bytes of each buffer, you need not use the partial flag at all.

For example, if your buffer size is 16384 bytes. You can just being to write to the buffer when full_flag is deasserted (indicating there is a buffer available to write to). You can write upto 8192 times (16 bit interface) to fill the buffer and then stop writing and wait for the full_flag to deassert again for the next buffer availability.

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