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Question regarding SPI in DMA mode | Cypress Semiconductor

Question regarding SPI in DMA mode

Summary: 1 Reply, Latest post by PRAG on 27 Oct 2014 07:13 AM PDT
Verified Answers: 0
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stz's picture
10 posts



I'm trying to develop an own second-stage bootloader based on the provided example from the SDK. In the example, the SPI is used in DMA mode for reading the (firmware) image from flash to be started (see function bootFromSpi()). The transfer size of the DMA is always the same and in the example set to 256 byte (SPI_DMA_XFER_SIZE).

To speed up the boot time I increased the maximum DMA transfer size to 4096 byte and adapted the demo in that way to set the transfer size to the maximum transfer size or if less bytes are to be read, to the remaining number of bytes. The remaining number bytes typically NOT 16-byte aligned. After these changes, the demo failed.

I found a hint in the FX3 Technical Reference Manual, chapter 10.21 SPI Registers, where the number of bytes in the registers SPI_RX_BYTE_COUNT and SPI_TX_BYTE_COUNT is restricted to 4-32 bits.

So my question refering to the hint in the TRM is: Does this mean, that DMA transfers have always to be 16-byte aligned?




PRAG's picture
Cypress Employee
173 posts

 Hi Stefan,


I know we have discussed this on the support case, but I will post here for the sake of completeness.

The buffers used for all DMA transfers in Fx3 need to be 16-byte aligned and a 16-byte multiple (size).



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