Question about AN87216 - GPIF™ II Master Interface | Cypress Semiconductor
Question about AN87216 - GPIF™ II Master Interface
Hi, I have read through the document of the application note AN87216 - Designing a GPIF™ II Master Interface, but I still cannot figure out the purpose of the GPIF data counter and address counter. They are set as 2048 for data counter and 256 for address counter. I am guessing the counter values are based on DMA buffer configurations, but what is the connection between these configurations? In the master GPIF state machine, what is the purpose of WR_DATA_WAIT and RD_DATA_WAIT states?