Problem with GPIF II in master mode | Cypress Semiconductor
Problem with GPIF II in master mode
I need to design FX3 as a bus-master to perform adressed reading and writing operations to external memory via A/D-MUX bus. But I don't understand perfectly how GPIF should differ if DMA wants to perform read or write operation. I tried to make GPIF project, where TH0 is for write operations, but TH1is for read operations. Initial IDLE state has two outgoing triggers: DMA_RDY_TH0 and DMA_RDY_TH1, which select and start read or write cycle. But GPIF II Designer shows error message "DMA_RDY_TH0 and DMA_RDY_TH1 cannot used together in the outgoing equations from the state IDLE ". I tried to do some experiments to workig around this error, but unsuccessfully.
Would you please help me to understand how to perform master reading and writing operations on A/D-MUX bus using Sockets? I attach the project to illustrate this problem.