A problem about USB 3.0 Slave FIFO mode | Cypress Semiconductor
A problem about USB 3.0 Slave FIFO mode
We encounter a problem with the USB 3.0 Slave FIFO mode. Any help or input on this is very appreciated.
The periheral equipment is FPGA , we use the internal clock . When the FPGA sends data at the frequency of 50MHz , it works well and the host can receive data successfully . We test the speed is about 190MB/s , but when we change the frequency to 100MHz , the host cant receive any data . I can't find the reason and the solution . Who can help me
By the way,our environment is C#(.NET) , and our chip is CY3014 , the OS is Win7 , 64 bits . We define the producer socket is Socket 0 and the consumer socket is Socket 3, the FPGA write data to address 0.