Please help : Doubling data coming through in Slave FIFO Interface project (ref.AN65974) | Cypress Semiconductor
Please help : Doubling data coming through in Slave FIFO Interface project (ref.AN65974)
Please advise me on the following issue.
I am running original CyPress slaveFIFO2b_streamIN FPGA project (Altera, Verilog).
In Streamer (cpp) I can see data , which come throug. It should be 32-bit (4x8 bit) numbers increasing by 1.
It is according to Verilog data generator :
if(slwr_streamIN_d1_ == 1'b0) begin
data_gen_stream_in <= data_gen_stream_in + 1;
Instead , I can see two instants of the same data , then one epoch is missing, like this:
01 00 A8 0D 01 00 A8 0D 03 00 A8 0D 03 00 A8 0D
All code is original, no changes.