Interrupt Endpoint | Cypress Semiconductor
Hi, i have setup an interupt OUT endpoint. All i want to do is once anything is written to the endpoint, an interupt signal is generated to the external processor(in my case the FPGA). In my case the FX3 is the master. Was wanting to know other then the descripters and epCfg calls, does anything else need to be setup? Also what pin on the development board can we probe this signal ?