I don't know why I received error data when I use FPGA to send data through Cyusb3014 | Cypress Semiconductor
I don't know why I received error data when I use FPGA to send data through Cyusb3014
Detail: The Cyusb 3014 work as SlaveFifoAsync mode and with 16bit databus . I send data as the AN65974 does , when my data is 100MHZ, the data I received are correct ,but if I send data with clock 20MHZ and teh data are like picture 1,every data may show 5 times; If I change the clock FPGA seng to Cyusb3014 as 20MHZ, we can see the simulation show in picture 2,and clk_out is the clock FPGA send to USB , but the control center may display like this: BULK IN transfer BULK IN transfer failed with Error Code:997,show in picture 3.
I really don't know how to solve it ,can anyone help me,thank you very much!