HOW does Asynchronous Sram firmware statemachine work?? | Cypress Semiconductor
HOW does Asynchronous Sram firmware statemachine work??
I'm testing the Asynchronous Sram firmware example( Cypress\SuperSpeed Explorer Kit\1.0\Firmware\SRAM_FX3) with the Super Speed Developer Kit under instructions on the " Super Speed Explorer Kit User Guide.pdf". It got worked .
But i just got to be confused about the state machine.
1. Firstly , We initialized the 'LD_ADDR_COUN ' ( counter load value = 0, counter limit value = 255 ,step = 1 ) just as default. Secondly , I wrote a 1024 Bytes hex into SRAM , then read it out and got all 1024 bytes data we wrote .
BUT it seemed that the write cycle actually happened 255 times( 0 - 254 ) ,not 256 times( 256* 32 bits = 1024 bytes ), what actually happened in the write cycle ? Did i understand correctly ?
2. To understand the issue mentioned above , we set the LD_ADDR_COUN 's counter limit value as followed (load value = 0,step =1), then read data out . we also print the debug msg with the USB-UART functionality.
you can get more detail in the attched file.
It can only be correct when the counter limit value is equal to 2^n-1, what does the "CYU3P_PIB_ERR_THR3_RD_UNDERRUN" mean ? And what's wrong?