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HOW does Asynchronous Sram firmware statemachine work?? | Cypress Semiconductor

HOW does Asynchronous Sram firmware statemachine work??

Summary: 1 Reply, Latest post by Manas on 10 Dec 2014 01:39 AM PST
Verified Answers: 1
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bat man's picture
6 posts

  I'm  testing  the Asynchronous Sram firmware example( Cypress\SuperSpeed Explorer   Kit\1.0\Firmware\SRAM_FX3) with the Super Speed Developer Kit  under instructions  on the " Super Speed     Explorer Kit User Guide.pdf". It got worked . 

   But i just got to  be confused about  the state machine.

1.  Firstly ,  We  initialized the  'LD_ADDR_COUN '  ( counter  load  value = 0,  counter limit  value  = 255 ,step = 1 ) just as default.  Secondly , I wrote a 1024  Bytes hex into SRAM , then read  it  out and  got all 1024 bytes data we wrote .    

   BUT  it seemed that  the write  cycle actually  happened  255 times( 0 - 254 )  ,not  256 times( 256* 32 bits = 1024 bytes ),  what actually happened  in the write cycle ? Did i understand correctly ?

2. To understand  the issue  mentioned above , we set the  LD_ADDR_COUN  's counter  limit  value  as followed (load value = 0,step =1), then read data out . we also print the debug msg with the USB-UART functionality. 

you can get more detail in the attched file.


   It can only be correct when the counter limit value is equal to 2^n-1, what does the                                       "CYU3P_PIB_ERR_THR3_RD_UNDERRUN" mean ?   And what's wrong?




Manas's picture
Cypress Employee
15 posts


We have a count of 255 because, the GPIF-II state machine checks for the condition before the action is executed. So when the count is 255, the condition will become true, but still it will execute the actions associated to the current state and then moves to the next state. So, actually it will runn for 256 times.





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