## Highest possible frequency for PWM mode in FX3 | Cypress Semiconductor

## Highest possible frequency for PWM mode in FX3

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10 Dec 2014 12:20 AM PST

#1
Hi all,

I have been using my GPIO pin as complex pin and running it in PWM mode as shown below, I am having my **PWM_PERIOD as 2** and **PWM_THRESHOLD as 1** to get** 50% duty cycle** and the maximum frequency I get through this is 32 MHz. Is there any possiblity to acheive higher freqencies ? and is there any conversion formula from gpioConfig.period to time in micro seconds ?

gpioConfig.pinMode = CY_U3P_GPIO_MODE_PWM;

gpioConfig.intrMode = CY_U3P_GPIO_NO_INTR;

gpioConfig.timerMode = CY_U3P_GPIO_TIMER_HIGH_FREQ;

gpioConfig.timer = 0;

gpioConfig.period = PWM_PERIOD;

gpioConfig.threshold = PWM_THRESHOLD;

apiRetStatus = CyU3PGpioSetComplexConfig(PWM_GPIO, &gpioConfig);

Hi,

Can you try these settings:

Clk_src = SYS_CLK = 384 MHz

Fast_clk = SYS_CLK/2

gpioConfig.pinMode = CY_U3P_GPIO_MODE_PWM;

gpioConfig.intrMode = CY_U3P_GPIO_NO_INTR;

gpioConfig.timerMode = CY_U3P_GPIO_TIMER_HIGH_FREQ;

gpioConfig.timer = 0;

gpioConfig.period = 3;

gpioConfig.threshold = 2;

Regards

Shashank

I did try them and get 48Mhz though its not exact 50% duty cycle theoretically.

Please answer the other part of the question... What is the highest possible frequency that can be achieved in this mode ? and is there any conversion formula for pwm period to micro seconds ?

Hi,

What are the exact timings for the high and low periods on your 48MHz signal?

The conversion is like this.

One count of the 'period' and 'threshold' field corresponds to one Gpio_Fast_Clk time period.

The count in the threashold field will determine after how many fast_clk periods would the PWM signal transition from low to high.

The count in the period field will determine after how many fast_clk period would the PWM signal transition from high to low.

Essentially, ((threshold+1)/(period+1))*100 would be the duty cycle. (the +1 is because the counts start from zero).

In most cases, fast_clk = 192MHz => fast_clk period = 5.2083ns.

You can determine the rest based on above explanation.

Theorectically, you should be able to generate a 96MHz signal here. But there is some issue with it.

So for now only 48MHz is the max possible frequency.

Regards

Shashank

Thanks for your reply. However I am unsure of what can I get from your reply.

What are the exact timings for the high and low periods on your 48MHz signal?Since I have said duty cycle is 50% its understood that high and low periods are just half of the required time period ie., 48MHz - 20.8333 ns and so high and low periods are 10.4166 ns each.

The conversion is like this.One count of the 'period' and 'threshold' field corresponds to one Gpio_Fast_Clk time period.The count in the threashold field will determine after how many fast_clk periods would the PWM signal transition from low to high.The count in the period field will determine after how many fast_clk period would the PWM signal transition from high to low.In most cases, fast_clk = 192MHz => fast_clk period = 5.2083ns.You can determine the rest based on above explanation.I use 19.2MHz input clock so sys clock is 384MHz and since min divider is 2, the available clock is 192MHz. As you mentioned above, if I need 10.4166 high and low periods, I should use 2 for period as well as 2 for threshold and since it starts from 0, I have 1 added to each so while I set the values it should be 1 each. Are you meaning to say that the above statement is correct ? or is there any additional time for high or low levels in addition to these transition times ?

Essentially, ((threshold+1)/(period+1))*100 would be the duty cycle. (the +1 is because the counts start from zero).How come this formula correspond to the above mentioned explaination ? If the above is true, then if high and low periods are the same then duty cycle is 50% which contradicts with the formula.

Apologize for the mistake.

This is the corrected version:

The count in the threshold field will determine after how many fast_clk periods would the PWM signal transition from

high to low(initial value is high).The count in the period field will determine after how many fast_clk periods would the PWM signal transition from

low to high(for the next PWM period). This count also signals the end of current PWM period.The point to note is that the threshold and period counts would begin at the same time (at the beginning of every PWM period).

Hence the formula ((threshold+1)/(period+1))*100 holds true.

Thanks again for the response. Now its clear.

So are you saying that any values below 3 for period or below 2 for threshold will not yield desired results ? I ask this because when I try period = 2 and threshold = 1, instead of getting 64MHz theoretically I get only 32MHz. And also is it because of this you recommend me to use 3,2 instead of 3,1 which is an ideal case for 50% duty cycle ?

Please let me know when this issue is solved.

Thanks, I appreciate your replies in this thread and It helped me a lot.

Yes, that is correct.

Ideally, for example, period=3 and threshold=1 should yield a 48MHz signal with 50% duty cycle. But we end up with a 24MHz signal with 50% duty cycle instead.

Although we cannot confirm, it looks like the output frequency is halved w.r.t the theoretical value when threshold<2.

We have tried a few combinations here and there is definitely a problem with threshold<2.

We have not yet identified what the issue is, we have reported it to the design team and it is being investigated.