GPIF Master Mode Problem | Cypress Semiconductor
GPIF Master Mode Problem
I have used a GPIF Master Mode example from another forum and altered it for my purposes. The big picture of what i want to do is have data being transferred from the USB port(master) to the GPIF and that data then sent out on the data bus to an FPGA. At the moment what i am having trouble with is i want to send some bytes (using the control center) to an OUT endpoint and that data then sent to the GPIF, then outputed 8 bit data bus (D0:D7 --> GPIO-GPIO). I also want to be able to recieve some bytes (using the control center) from an IN endpoint. I want the GPIF to not interfere with any data and just let the data pass to the data bus.
The main problems i am having are:
1) How should the 2 endpoints/sockets be setup
2) What DMA channel (i.e AUTO,MANUAL, etc..) should be used.
3) Do we use IN_DATA action or DR_DATA action in one of the states in the state machine.
4) Do i use socket or register in the 2 actions above.
Ive been trying for weeks now and i cant seem to get it working, so can someone please help me that would be much apreciated.