FX3 Synchronous Slave FIFO Interface 32-bit Data / 5-bit Addr : How to notify FPGA that data is to be read on a perticual socket? | Cypress Semiconductor
FX3 Synchronous Slave FIFO Interface 32-bit Data / 5-bit Addr : How to notify FPGA that data is to be read on a perticual socket?
We are new to the FX3 and we wish to use the GPIF II in Synchronous Slave FIFO Interface 32-Bit Data / 5-bit Address.
Our product architecture shall allow maximum bandwidth both ways (in and out of GPIF) and we wish to be able to access all socket to implement multiple end points. Board layout and FPGA/FX3 code was not written yet so we can change our mind on the GPIF II interface type and addressing mode.
I went thru AN68829 explaining how to access all 32 logical sockets but I still don't know how to notify the FPGA connected to the GPIF II on the incomming data (FX3 to FPGA) on a perticual logical socket.
So, how, for example, can I notify FPGA (the GPIF master) in a performant way to read socket 27?
- Add 5 output pins from FX3 for socket ID : Not enought pin left as per GPIF II Designer.
- Time multiplex Address and Data bus to gain those 5 pins? What is the impact on performance.
- Implement PP_Mode = 1 to use the RD mailboxe? This leaves only one thread on the GPIF and will impact performance.