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FX3 Synchronous Slave FIFO Interface 32-bit Data / 5-bit Addr : How to notify FPGA that data is to be read on a perticual socket? | Cypress Semiconductor

FX3 Synchronous Slave FIFO Interface 32-bit Data / 5-bit Addr : How to notify FPGA that data is to be read on a perticual socket?

Summary: 4 Replies, Latest post by wye1102 on 14 Jul 2016 04:51 AM PDT
Verified Answers: 0
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yreid's picture
3 posts

 We are new to the FX3 and we wish to use the GPIF II in Synchronous Slave FIFO Interface 32-Bit Data / 5-bit Address.

Our product architecture shall allow maximum bandwidth both ways (in and out of GPIF) and we wish to be able to access all socket to implement multiple end points. Board layout and FPGA/FX3 code was not written yet so we can change our mind on the GPIF II interface type and addressing mode.

I went thru AN68829 explaining how to access all 32 logical sockets but I still don't know how to notify the FPGA connected to the GPIF II on the incomming data (FX3 to FPGA) on a perticual logical socket.


So, how, for example, can I notify FPGA (the GPIF master) in a performant way to read socket 27?


Explored ideas:

- Add 5 output pins from FX3 for socket ID : Not enought pin left as per GPIF II Designer.

- Time multiplex Address and Data bus to gain those 5 pins? What is the impact on performance.

- Implement PP_Mode = 1 to use the RD mailboxe? This leaves only one thread on the GPIF and will impact performance.

mady's picture
Cypress Employee
964 posts



The only way to notify FPGA about the data coming in which socket is to have Flags coming out of FX3. The FPGA should change the address lines in a time division mux manner to check the state of flags everytime. If flags indicate that datat is present on a socket, the FPGA should stick to that address and get the data from the datat lines.

But there is a drawback with 5 Bit slavefifo. There is a considerable delay in switching from one socket to another which is dcoumented in the following KB article:


- Madhu Sudhan

wye1102's picture
8 posts


Previously we only use 4 endpoints to communicate with hosts. But in our new design there're 12 endpoints to be used. So there's the problem with EPSWITCH# signal. 

(1) Is that FLAGA will always toggle when EPSWITCH# is asserted? Can I just monitor FLAGA toggle to indicate address changed?

(2) What is the behaviour of FLAGA when the buffer is unavailable (e.g. an empty EPOUT endpoint)?


yreid's picture
3 posts

 So it means that if I poll empty consumer sockets (current flag always 0) I have to wait a hard 50 clock cycles since I will see no transitions on the flag. If the consumer socket is not empty, I can procedd with data reading on the flag transition to 1 (transition may occur before 50 clock cycles)?

stz's picture
10 posts



I have a  similar question regarding FX3 Synchronous Slave FIFO 32-bit Data and 5-bit address:

Is it possible to multiplex the data with the address lines to gain the 5 address pins for usage as flags?

With this setting, it would be possible to have dedicated thread flags (full/empty as well as partial) for any thread.




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