FX3: How does I2C multi-master behave, how to initialize it? | Cypress Semiconductor
FX3: How does I2C multi-master behave, how to initialize it?
I've got some difficulties to add a second master to the (400 KHz) I2C-bus, where FX3 used to be the single master up to now (using I2C-GPIO58_SLC and I2C-GPIO59_SDA with the standard I2C API). FX3 is said to be multi-master capable, so I've got some questions on its setup and behaviour:
Need multi-master to be specially enabled or is it just there.
What is the behaviour of FX3 during the bus-free time? Besides the specified minimal bus free time of 1.3 us, I found no other information in the specification. How does the I2C multi-master vary the bus-free time or generally behave at or after collision?
For testing, I establish a very greedy second master which continuously grabs the bus after a bus free time only slightly above the minimum (~1.57us, minimum is 1.3us), the traffic I start on FX3 is a simple I2C write with two bytes (to the same salve address, but different write bytes). I'd expect the FX3 to either start earlier than the FPGA master, keep quiet or a data collision to occur in the first write byte latest. However, it seems to pull low SCL eventually at very strange positions (after FGPA-master has released it high, but prior to the SCL minimum high period being terminated). This happens at all possible positions, sometimes after a very long traffic (e.g. Start-SlvAddr-Write-Restart-SlvAddr-Read, collision in the 8th read byte, pulling low SCL 80ns after release high by the other master) where FX3 must be aware that the bus is busy. Is there an explanation?
Thanks for your hints!