FX3 GPIF Address Problem | Cypress Semiconductor
FX3 GPIF Address Problem
I am working on making a firmware that is a master to an FPGA. In the GPIF II state machine, the address is driven to the address bus when DMA_Thread_0 is ready. From there, data is either driven or read from the data bus, depending on whether the FPGA sends a read-ready or write-ready signal, which it sends to the FX3 based on the address that it reads (the addresses are supposed to correspond to different FIFOs on the FPGA; half of the FIFOs read from the FX3, and half write to the FX3. The address it reads determines which FIFO should be accessed, and thus, which operation should take place).
The problem currently is that there does not seem to be any addresses driven to the address bus. Using the debug port, I have read that the DMA channels are indeed being configured and created. I am trying to use Control Center to send or receive data from an endpoint, and I am expecting the address to change once I do a bulk transfer in or out. However, I do not see any such address change on the logic analyzer I am using.
I have 6 endpoints set up (3 producer, 3 consumer), and 6 DMA auto channels.
I am using CY_U3P_PIB_SOCKETs 0, 4, 8, 12, 16, and 20; these should all be on thread 0 (so that I can use DR_ADDR from thread 0 in the GPIF state machine).
I am using CY_U3P_UIB_SOCKET_PROD 1-3, and CY_U3P_UIB_SOCKET_CONS 1-3. These, along with the 6 PIB_SOCKETs, are being used in the 6 CyU3PDmaChannelCreate() calls. I also use CyU3PSetEpConfig() and CyU3PGpifSocketConfigure() 6 times each.
Any ideas as to why the addresses are not coming up?