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FX3 (CYUSB301X) Slave FIFO timing waveform | Cypress Semiconductor

FX3 (CYUSB301X) Slave FIFO timing waveform

Summary: 1 Reply, Latest post by PRAG on 23 Oct 2014 04:52 AM PDT
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mjb's picture
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Hello, In the CYUSB301X RevP datasheet (and previous versions, also in AN65974) is there a mistake in the sync slave FIFO read sequence (Fig3)? The diagram shows 3 reads: a single access followed by a burst of 3. Should the data out triggered by the 2nd SLOE# falling edge be D_N(An) and not D_N+1(An) - ie the databus ouputs the last read value from An. The 3 read burst that starts at the same time as the 2nd SLOE# falling edge produces D_N(Am) thru D_N+2(Am) with 2 cycle delays as expected.

PRAG's picture
Cypress Employee
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It works this way:

SLOE acts as the final gate to the bus driver that drives out the data being pointed to.

SLRD increments the pointer each time it is asserted during a positive clock edge.


In the waveform, when the second SLOE falling edge occurs, the bus driver is activated and it drives out the last active data. In this case, the last active data is D_N+1(An). This is because the SLRD signal was asserted for one clock cycle prior to this wherein the pointer incremented and now points to D_N+1(An), not D_N(An).



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