FX3 (CYUSB301X) Slave FIFO timing waveform | Cypress Semiconductor
FX3 (CYUSB301X) Slave FIFO timing waveform
Hello, In the CYUSB301X RevP datasheet (and previous versions, also in AN65974) is there a mistake in the sync slave FIFO read sequence (Fig3)? The diagram shows 3 reads: a single access followed by a burst of 3. Should the data out triggered by the 2nd SLOE# falling edge be D_N(An) and not D_N+1(An) - ie the databus ouputs the last read value from An. The 3 read burst that starts at the same time as the 2nd SLOE# falling edge produces D_N(Am) thru D_N+2(Am) with 2 cycle delays as expected.