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FX3 Bulk in Endpoint bad data for first 1K of transfer | Cypress Semiconductor

FX3 Bulk in Endpoint bad data for first 1K of transfer

Summary: 1 Reply, Latest post by Madhu Sudhan on 26 Feb 2015 12:49 AM PST
Verified Answers: 0
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jbn60's picture
2 posts

I have a FX3 super speed explorer board connected to a Xilinx KC705 FPGA development board. I am wanting to bulk read data in  from the KC705 FPGA and created a GPIF project to do that based on John Hydes GPIF Example8 project (from his book SuperSpeed Device Design by Example). The problem I have is the first 1K bytes (or whatever my DMA buffer size is set to) are all 0
when the Transfer Data In command is issued in the USB Control Center. The data I am expecting and I have verified with a logic analyzer is not seen in the USB Control Center panel until 1024 + 12 Bytes (when I use a 1K buffer size) down in the display.

I have attached the frimware files for this project. I am puzzled as to why the data I am expecting is not seen until 1 buffer (1K) down in the data display.


mady's picture
Cypress Employee
964 posts

 Hi Jeff,

This is Madhu who is handling your case now. 

I went through your state machine and Scope diagrams. As you mentioned, it is strange why the TH0wait flag is asserted even in the beginning. We should check whether, for some reasons, the State machine has gone all the way upto STATE5, even before the FPGA has started sending data. If this was the case, then we would have got a buffer full of zero.

Can you please remove DR-GPIO Th0Wait action from the last state and see if you still see that flag high when you start the Chipscope? By this we can know whether the pin was shown high because of actual transition to STATE5 or because of some other reasons.


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