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FX2LP slave FIFO timing | Cypress Semiconductor

FX2LP slave FIFO timing

Summary: 3 Replies, Latest post by andrewsobotka on 30 Jul 2014 01:27 PM PDT
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subpixel's picture
2 posts

I am working on project using CY7C68013A in slave FIFO mode with FPGA. I need to use frequency 48MHz. I am not sure if the AN61345 (source file fx2lp_slaveFIFO2b_streamIN_fpga_top.vhd) meet all timing requirements of CY7C68013A for IFCLK 48MHz. Setup time of SLWR for externally sourced IFCLK is tSWR = 12,1ns and max clock to FLAGS output propagation time is tXFLG = 13,5ns. Output signal slwr_n is combinational, based on the state machine state and flagd. It seems to me that setup time of SLWR can't be met. It is possible to use 48MHz externally sourced IFCLK and write data to cypress chip by the use of burst mode (SLWR asserted continuously)? I need to watch Full Flag of FIFO and immediately react to it (combinational function of some internal signals and Full Flag), right?

VAVC's picture
Cypress Employee
506 posts

Hi ,


The AN61345 is tested with Spartan 6 board interfaced with FX2LP. The project works fine.


The things what you have mentioned for burst mode is already implemented in the FPGA code.




subpixel's picture
2 posts


thanks for your fast response. My project seems to works fine too. But I would like to have everything ok for serial production. It is not sufficient for me to have few working samples in laboratory environment. As I said before, it seems to me, that timing requirement is not met in AN61345.

Fpga output signal SLWR is combinational function of some internal signals and input signal FIFO_FULL (flagd). FLAGS output propagation time from FX2LP is tXFLG  = 13.5ns. So only this propagation time cause that setup time for SLWR tSWR = 12.1ns (minimum time for stable signal before active edge of the clock) can't be met for TCLK = 20.083ns (without calculating with propagation time of signals through the PCB, FPGA IOBs, internal logic delay, etc). Only way to meet tSWR requirement is with one clk period delay, but it can cause writing to FULL fifo.

If I am wrong, please help me to understand this. Thanks 

andrewsobotka's picture
44 posts

hi subpixel,

Please look at the EZ-USB TRM for the EPxFIFOCFG registers.  I think you will find bit 6, INFM1, to be useful.  It causes the Full flag to be set one clock cycle early.  This should allow you to reach timing closure.


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