FX2LP slave FIFO timing | Cypress Semiconductor
FX2LP slave FIFO timing
I am working on project using CY7C68013A in slave FIFO mode with FPGA. I need to use frequency 48MHz. I am not sure if the AN61345 (source file fx2lp_slaveFIFO2b_streamIN_fpga_top.vhd) meet all timing requirements of CY7C68013A for IFCLK 48MHz. Setup time of SLWR for externally sourced IFCLK is tSWR = 12,1ns and max clock to FLAGS output propagation time is tXFLG = 13,5ns. Output signal slwr_n is combinational, based on the state machine state and flagd. It seems to me that setup time of SLWR can't be met. It is possible to use 48MHz externally sourced IFCLK and write data to cypress chip by the use of burst mode (SLWR asserted continuously)? I need to watch Full Flag of FIFO and immediately react to it (combinational function of some internal signals and Full Flag), right?