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DMA controller overrun | Cypress Semiconductor

DMA controller overrun

Summary: 2 Replies, Latest post by eniv4 on 18 Dec 2015 07:16 PM PST
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eniv4's picture
13 posts


Does someone know what is the meaning of PIB error: CYU3P_PIB_ERR_THR0_ADAP_OVERRUN. Only note I found about it is from the source code (cyu3pib.h):
DMA controller overrun on a write to one of the Thread 0 sockets. This typically happens if the DMA controller cannot keep up with the incoming data rate.

It is different than the more common error: CYU3P_PIB_ERR_THR0_WR_OVERRUN, which means writing to a full buffer.

Thread0 in the PIB deals with an auto DMA channel between the host and the GPIF-II. I get this error seldom. Is there anything I can do about it?



PRAG's picture
Cypress Employee
173 posts

Hi Eyal,

The error you face here is CYU3P_PIB_ERR_THR0_ADAP_OVERRUN. The error indicates that the DMA controller itself is not able to keep up with the incoming data rate. The only scenario where we've seen this before was when the DMA controller was being run at a clock speed lower than 100MHz, but the GPIFII interface itself was clocked at 100MHz. This was fixed by ensuring the Fx3 system clock is running at 400MHz, which meant the DMA clock was 100MHz.

Please ensure this is the case in your firmware as well (by setting setSysClk400 to CyTrue if your GPIFII frequency is 100MHz).

Theoretically, this could also happen in such a situation: If the CPU is performing some tasks that would require DMA cycles while the GPIFII is simultaneously trying to fetch/drive data from/to the FPGA, it could potentially mean that the DMA is being starved of bandwidth to dedicate to the GPIFII domain's transfers. If this is true, then cutting down some DMA-intensive code (thereby dedicating the DMA controller to the GPIFII) from your firmware should help alleviate this problem.


eniv4's picture
13 posts

Thanks PRAG.

I do have the FX3 system clock configured for 400MHz, where CPU, DMA & MMIO clk dividers are all set to two.
1.PIB to UIB DMA channel is auto without CPU intervention. Is it still possible that the DMA will not have enough bandwidth?
2.Would a similar symptom arise if the GPIFII interface is slightly over clocked, for example 100.5MHz instead of 100MHz?


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