CY7C68000 UTMI 16 bit data bus, signals error. Help ! | Cypress Semiconductor
CY7C68000 UTMI 16 bit data bus, signals error. Help !
I am debuging my USB system. It is 3C80 FPGA + CY7C68000 USB PHY. The problem is that USB communication don't stable. It is OK in first several seconds, then disconnect with USB Host. Capturing 2 photo of the UTMI signals as follow.
Picture 1 & 2,
Channel 4 is 30MHz PHY CLK. Channel 3 is RxValid.
There is difference clock to control out time on RxValid. One is about 5ns, another about 12ns. And there is a ~10ns low pulse on RxValid of picture 2. I think it's the point of my problem in picture 2. I try to find out why RxValid so strange, but fail.
Any suggest to debug my USB connect?