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clock reduction malfunction | Cypress Semiconductor

clock reduction malfunction

Summary: 1 Reply, Latest post by Madhu Sudhan on 24 May 2015 09:32 AM PDT
Verified Answers: 0
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user_367131467's picture
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Hello Dear friends

My Fx3 Dvk doesn't work properely when reduce input clock frequency from peripheral , its programmed with SlaveFifoAsync and it's ok on streaming data recieved from peripheral down to 50Mhz speed . but after decrease from 50MHz it fails to deliever given data .



mady's picture
Cypress Employee
963 posts


Do you mean when you reduce the frequency of the clock source of the Master (external device that you connect to FX3), you are not able to do data transfer? Please clarify?

If so, haveyou verfied that the external master is working properly on that frequency?


- Madhu Sudhan

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