AN65974 - Slave FIFO - Sampling Regarding | Cypress Semiconductor
AN65974 - Slave FIFO - Sampling Regarding
I have been working in AN65974 Sync Slave FIFO Interface. I am using an Altera FPGA as an master and FX3 as an Slave. For 100MHz I am facing Data Integrity issues. So, I need to change the data sampling point from Positive edge to some delay after positive edge. How to do that or is that not possible. Please Help.
Gokul Prasath N