[68013A]Why missing some bits in a bluk? | Cypress Semiconductor
[68013A]Why missing some bits in a bluk?
Summary: 10 Replies, Latest post by dtysky on 11 Mar 2014 07:42 PM PDT
Verified Answers: 0
09 Mar 2014 12:38 AM PST#1
I just want to use the “slave-fifo” mode to connect PC and FPGA.
But when i get data from Cy68013A to FPGA , it works not well.
i use 512-bytes X 4 in EP2 ,out ( i have tried to use 1024-bytes X 2 mode,but it can’t work ) , and get a 1024-bytes bulk every turn.
Every turn i get it will miss some bits , probably one or two or three...and it will get some data from next bulk.
And...even though it transfer successful in frist turn , next turn the XferData aslo probably return "false".