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CY7C67300 Interrupt Vector | Cypress Semiconductor

CY7C67300 Interrupt Vector

Summary: 1 Reply, Latest post by PRJI on 27 Aug 2012 05:18 AM PDT
Verified Answers: 0
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BitHammer's picture
1 post

Hi Group.

This may seem a very basic question. I am trying to fix a lockup in cy7c67300 software system written by another person, in assembly code.  I understand the interrupt vector system as explained in the data sheet ("EZ-Host provides 128 interrupt vectors. The first 48 vectors are
hardware interrupts and the following 80 vectors are software
interrupts....")  What I see in the software is that for instance the address of the ISR for timer1 is loaded to address 0x0002, the ISR address for GPIO irq 1 is loaded to address 0x0006, and in assembly code:

    mov        w[0x0004],CY_GPIRQ0        ; set interrupt vector for GPIRQ0

All of this is very fine.   What is not yet revealed to me is the mapping of the rest of the interrupt vector table.  Where is this written down? In other words, what hardware event is mapped to each of the 48 ISR vectors?


I have the cy7c67300 data sheet,  the CY16 USBHSC Risk Programmer's Guide, but neither of these show the detailed map of the interrupt vector table.


Thanks in advance for any illumination.


prji's picture
Cypress Employee
473 posts


 Please go through ISRS.S file in Common folder.




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