Why the length of WR_FIFO is longer than what I want? | Cypress Semiconductor
Why the length of WR_FIFO is longer than what I want?
Summary: 1 Reply, Latest post by Shub on 02 Mar 2011 03:20 AM PST
Verified Answers: 0
01 Mar 2011 09:15 PM PST#1
I use the 68013A, GPIF mode, the FIFO write, found that each write of n data , the length of WR_FIFO signal is longer than n datas' length, the result is that n+1 datas wrote into the FIFO. why ?