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WaitForXfer() problem in BulkLoopDlg.cpp with CyApi.lib | Cypress Semiconductor

WaitForXfer() problem in BulkLoopDlg.cpp with CyApi.lib

Summary: 3 Replies, Latest post by acorrd on 27 Aug 2011 08:24 AM PDT
Verified Answers: 0
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acorrd's picture
12 posts


I'm working our project with cybulk example which is located in

c:\Program Files\Cypress\Cypress Suite USB 3.4.2\CyAPI\examples\cybulk\  .

And MCU (CY68013A) code is refered on c:\Program Files\Cypress\GPIF Designer\fifo\ .

Structure is below.

host sends cmd by ep0 for uploading 32MB. -> mcu set GPIF and others in TD_Poll().

Now, WaitForXfer() has some bug. in previous  bulletin, somenoe had same problem.


you can compare below 3 codes. it is extracted from BulkLoopDlg.cpp.

- WaitForXfer() has expired time every test. 

- if TD_Poll() function is continuously uploading , WaitForXfer() will be success.

 in oscilloscope , GPIF counter has 6 cycle completely, but WaitForXfer() has complete 

  receving then. 

 Maybe, BeginDataXfer() doesn't set event , when it has received by Length argument.

current correctly return of WaitForXfer() is returning by over received or other problem.

if you test this problem, don't operate example directly.

example code for MCU is wrong. it uploads infinitly by IN packet. Thus it fake bulkloop codes of WaitforXfer() as

correctly operation.





UINT XferLoop(){


#if 0//original code
     UCHAR  *outContext = dlg->OutEndpt->BeginDataXfer(data,outlen,&outOvLap);
     UCHAR  *inContext = dlg->InEndpt->BeginDataXfer(inData,inlen,&inOvLap);
        success = dlg->OutEndpt->FinishDataXfer(data, outlen, &outOvLap,outContext);
        success = dlg->InEndpt->FinishDataXfer(inData,inlen, &inOvLap,inContext);

#elif 0//modified to use Bulkendpoint instead Endpoint class. it is still using WaitForXfer().

  //UCHAR  *inContext = dlg->InEndpt->BeginDataXfer(inData,inlen,&inOvLap);
  UCHAR  *inContext =dlg->USBDevice->BulkInEndPt->BeginDataXfer(inData,inlen,&inOvLap);
  SendCmd(VX_B3);// send upload command by ep0. it release once  if(in_enable) variable in 

Fx2_to_extsyncFIFO.c file.

        //success = dlg->InEndpt->FinishDataXfer(inData,inlen, &inOvLap,inContext);
  success = dlg->USBDevice->BulkInEndPt->FinishDataXfer(inData,inlen, &inOvLap,inContext);

#else //this is good!!

  //UCHAR  *inContext = dlg->InEndpt->BeginDataXfer(inData,inlen,&inOvLap);
  UCHAR  *inContext =dlg->USBDevice->BulkInEndPt->BeginDataXfer(inData,inlen,&inOvLap);
  Sleep(400);//32MB is consume about 349.5ms. 349.5ms/20.83ns=16M WORD.  //it is correct.

  //success = dlg->InEndpt->FinishDataXfer(inData,inlen, &inOvLap,inContext);
  success = dlg->USBDevice->BulkInEndPt->FinishDataXfer(inData,inlen, &inOvLap,inContext);






acorrd's picture
12 posts



in my test, I found sudden fact.

BeginDataXfer() and WaitForXfer() are well operate with 512 byte length.

but above 512 length has many problems.

is it correct?

our project is transffering 32MB per acquisition.

thus I coded BeginDataXfer(buffer pointer, 32000000, &inOvLap).


aasi's picture
Cypress Employee
1166 posts

What is the error you're getting? In the code that you have working you've a 100ms delay which you don't have in the other 2 code which you claim as not working. Have you tried the other 2 with this 100ms delay?



acorrd's picture
12 posts

Dear aasi,

Above problem is my mistake.

I've studied GPIF document exactly, and now, I'm using the Flow State to transfer 32MB data to host by EP6IN.

It is very simple method.

But two problem left.

1. CTL0 is used for external fifo. Data out clock for external fifo and Data fetch clock for cy7c68013.

    in my test, I 1,048,576 byte are transferd. GPIF counter was set by 524,288 with 16 bit data bus of cy7c68013.

   But CTL0 clock is presented 524287 . It was measured Logic analyzer.

   Other sizes are same with problem.

  In begin transfer, 68013 fetch 1024 clock , because internal EP6IN buffer is 2048 bytes.

   and after some miliseconds, it is starting main transfering.

 But at this point, 68013 fetchs 1023 clock only. !!!!

Thus Last total clock of CTL0 is the Total GPIF Counter - 1.

Why does it take minus one of Buffer size ?

  I've tried to clean endpoint fifo. 0x80 -> reset each fifo -> 0x00  as Data sheet and Example code.

But it is lack One clock still.

 And Host program and USB protocol monitor has presented number of data as GPIF counter.

My test method without complete FPGA and other circuit is,

    upload 1MB to host . use break point of Visual C. WaitForXfer() and Finish() has correct return value.

    with USB protocol monitor  , I can see entire data . It has 0xff , because 16 data pins are weak pull up internally.

  -> some pins are shorted to ground , logic level is zero.

  -> upload re-try.

  -> compare entier received buffer contents with previous 0xff. Entire buffer has replaced with different value.


  with fifo reset codes, I've succedded data changing each upload.

 But CTL0 pin toggling is lack One clock Only.

if you can't understand my environment and problem , I can describe more kindley.


Best regards,


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