Slave FIFO OUT throughput | Cypress Semiconductor
Slave FIFO OUT throughput
We have a design with an FX2 (CY68013A) and an FPGA. We use the Slave FIFO interface and are mainly interested in high OUT throughput.
I currently have around 27 MB/s but the screamer example says it can do 32 MB/s. On the PC side I already have everything as in the screamer example, I think.
I use a programmable flag for almost empty so I can keep SLRD active continuously for most of the transfer between FX2 and FPGA.
I'm using 4x 512 Bulk mode on EP2 and EP6.
I'm using an external IFCLK running at 40MHz.
Where should I look for improvement? Internal instead of external IFCLK? Faster IFCLK?
I also found out that when I use two devices the combined throughput can go up to 41 MB/s. Why can't a single FX2 get this bandwidth?
Any help is appreciated,