slave FIFO interface -- how to detect end of USB transfer ? | Cypress Semiconductor
slave FIFO interface -- how to detect end of USB transfer ?
In our application network packets having a size between < 512 bytes up to 15xx bytes are sent from the USB host over a slave FIFO interface to an FPGA using bulk transfers. The USB bulk endpoint operates in autoout mode without CPU intervention.
A major problem has been the detection of the end of a USB transfer. Currently, the FPGA monitors the empty flag of the USB out FIFO for a packet < 512 bytes.
Example: The host sends a network packet of 1200 bytes. The FPGA reads USB bulk packets of 512, 512 and 176 bytes. The 176 byte packet tells the FPGA that the USB transfer ends.
However, this approach has two problems.
a) If the host sends the packets very fast, two USB transfers are stuck together. For example, if the host sends two packets of 1200 bytes, the FPGA may receive packets of 512, 512, 512, 512 and 352 bytes.
b) The FPGA has to read out any arriving packet IMMEDIATELY. Otherwise, problem a) occurs. This requires additional flow control between host and FPGA.
Is there a better way of solving this framing problem when using the FIFO slave interface ?