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regarding configuring the controller as slave fifo mode | Cypress Semiconductor

regarding configuring the controller as slave fifo mode

Summary: 2 Replies, Latest post by andrewsobotka on 20 Apr 2009 03:54 PM PDT
Verified Answers: 0
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vishal's picture
1 post


I am new to design side. so can u please help me out?

I am using CY7C68013A.

i want to interface controller with fpga using slave fifo interface. but i do not know how to configure the controller and what data content should i write into controller registers to set it as a slave fifo? How can i configure the controller? Do i have to use any EEPROM to configure the controller? If so, then what registers value i have to load in EEPROM? And how EEPROM will configure the controller?

Thanks & Regards

aasi's picture
Cypress Employee
1166 posts

Download the technical reference manual of fx2lp... it has code snippets to implement slave fifo (actually 90% of the code)...

andrewsobotka's picture
44 posts

aasi is correct, the Technical Reference Manual for the FX2LP is the primary bible for any FX2 developer. It's a huge document.

Additionally, if you are using an FPGA, I highly recommend looking at the actual FX2LP datasheet. There is so much information in the TRM that one often forgets about what's in the datasheet. There is a wealth of timing information, including some anomalies regarding FIFO interface. For example, the setup and hold times for the Slave FIFO pins changes drastically depending on whether the IFCLK is internal or external. Another example is that the FIFO address bus' setup time is greater than one IFCLK cycle at 48 MHz. Finally, it shows timing diagrams for burst reads and writes to the slave FIFO interface.

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