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Reading data from FPGA via cy7c68013a | Cypress Semiconductor

Reading data from FPGA via cy7c68013a

Summary: 4 Replies, Latest post by prophet36 on 12 Sep 2012 06:31 AM PDT
Verified Answers: 0
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Sammy555's picture
3 posts

Hi all, I'm new to USB development and really hope I can find some help here.

I'm working on developing a board which has already been fabricated and populated with the CY7C68013A-128AXC.

I need to read out data from from FPGA RAM to a host application. (I've been using VC ++ 2010 to try to do this)

Ports PB and PD are my 16 bit data lines from the FPGA to fx2.  Ideally I want flaga and flagb to go high to inisiate read and write oporations in the FPGA, but most important for me is passing the data from port PB and PD, and initiating a 48Mhz clk from IFCLK. I've tried AN61345 however the FIFOADR pins are not connected to anything on my board, so I assume the example will not work.

Is is possible to write my software to configure the cy76c8 registers to properly handle the data transition and IFCLK when run? 

Thus far, using CYAPI.lib I have not been able to recieve data from the FPGA. Any help is appreciated.



rskv's picture
Cypress Employee
1134 posts

Hi Sam,

As per my understanding, following is your setup.

FPGA --> FX2LP acting as slave --> PC.

If you are just concentrating on transferring data from FPGA to PC then you could do the following thing. You can connect FIFOADR1 to High and FIFOADR0 to 0/Ground, if you are planning to use the same example project without modifying.

Otherwise, if you are going to modify the firmware so that EP2 acts as an IN endpoint then you can connect those to pins to Ground.

Please let me know if that does not solve your problem.


sai krishna.

Sammy555's picture
3 posts

Thanks for you repy,

what should I modify in the AN61345 uvision project file to set EP2 as an IN endpoint? Do you recomend the fx2_trm as the best reference for making these sort of modifications? 

Sammy555's picture
3 posts

In my verilog code I've permanently deasserted the read and fx2 fifo output enable bits, and permanently asserted the fx2  fifo write bit.  I'm using a virtex 4 and havnt yet ported over the hdl code supplied in the example to try.

In the AN61345 firmware I switched the configuration values for EP2 and EP6, and changed EP6AUTOIN to EP2AUTOIN.

I'm  not seeing any data in my input buffer when I make a asyncrounous transfer as outlined in the cyapi programers reference.

Hmm this is tough, maybe I should slow down and take a step back to figure this one out (if only I had the time) 

Thanks, any advice is appreciated



prophet36's picture
13 posts

You might want to take a look at FPGALink:

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