Problems reading data from my EP6 OUT endpoint | Cypress Semiconductor
Problems reading data from my EP6 OUT endpoint
I ran into some problems last 3 weeks while trying to implement the salve fifo synchronous read module on my fpga using verilog.
AIM of this project:
Transfer data from PC(matlab file) through c# program(using xferdata()) to the cypress usb. FPGA implements a read module to read data from EP6 and save in a FIFO-memory(IPCORE) for further processing.
After setting the SLOE(active low) and SLRD(active low) as required(Cypress manual), the data on the BUS doesn't really change. I used Chipscope from Xilinx for debugging and i got the following simulation(see pdf file).
As u can see from the simulation, although sloe and slrd shows that different values where supposed to be put on the bus, only 7373 is present at all times. why?
note: the status signal in the simulation is used to make sure that the slrd signal is asserted for exactly one clock circle meaning the cypress usb-device(Fx2) should increase pointer to next value in fifo(EP6) and sloe means it should move into the fd_bus.
-The usb_fd bus usually shows a different value that was never transmitted.(FD99)why?
-after resetting the usb device, the usb_bus shows 7FFF (I used 16 bits bus)why?
-I also noticed that when I changed the REVCTL = 0x03 in the TD_Init(), my endpoint doesn't work. USB Control Center throws an error (BULK OUT transfer ,BULK OUT transfer failed with Error Code:997) but when I comment it out, it works fine. (EP2 is of no use to me at the moment)
Please guys I have been working on this for weeks and I really need urgent help.
Any help will be greatly appreciated
Thanks in advance