Problem with Gpif-mode with external clock-source. | Cypress Semiconductor
Problem with Gpif-mode with external clock-source.
I'm working on a project, where we connected an Aptina optical sensor to the FX2 in GPIF-mode with external clock-source.
the LINE_VALID to RDY0,
the FRAME_VALID to RDY1
the pixel-clock to the IFCLK
and the pixel-data bus to D0-D7
pins of the FX2.
It works really well on the CY3681 developmen-kit with an rather old revision of the FX2 with 128-pins.
However on other board, with rather new FX2LP with 56-pins, the GPIF-wave once started will never get done, when I source the GPIF from the external clock-source (sensor generated pixel-clock).
When I experimentally switch the GPIF clock-source to internal clock, the wave will get done. In this case, the data are nonsense (because the GPIF is not synchronized to the pixel-clock) but I can see that my decision states (waiting for the start of the frame and start of the line) works...
On both boards I have connected the logic analyzer to the respective pins of the FX2 and can see that the signals from the sensor are the same. On the development-board, I see the states of the wave changing too. This I can't verify on the other board with the 56-pin version of FX2.
Can anybody please give me any hint, where else I should look?
Are there any specific differences between the different versions of the FX2, that might cause such a problem?
Any help is greatly appreciated.