Problem with CPU access endpoint data | Cypress Semiconductor
Problem with CPU access endpoint data
Im using FX2LP with endpoint 2 and 4 configured as BULK OUT double buffered 512 byte in MANUAL mode, and EP 6 and 8 configured as IN endpoint ISOCRONOUS double buffered 521 byte. Data are sent from PC, FX2LP CPU access data and commit manually all data packets to an external device accessing data through slave FIFO.
I have a strange beahviour whn PC host is sending data to OUT endpoint:
When FX2LP receive an OUT transfer from PC, ep2inout or ep4inout interrupt is triggering - depending from ep target -, and CPU make some access to fifo data, then commit data to slave fifo. Sometimes, when I have an element in fifo and when two packets are coming closely in time (about 100 uSec) CPU read data from endpoint fifo buffer but some data are from first packet, and other data are from second packet. It seems that, while CPU extracts data from endpoint fifo, data are changing. It seems that data packets is copied in fifo buffer from USB even if I have not committed packet, and endpoint is in manual mode. Before access data I verify that fifo is not empty with EP2468STAT register and I commit data only at the end of cpu accesses.
If I examine usb traffic with LeCroy T3 advisor protocol analyzer, I see that second packets has an initial NYET, then it seems ok, and only after time it receives an ACK.
I have an external microcontroller that extracts data from slave fifo, and it receive data packets correctly, then data are correct in fifo buffer, there is only problem with CPU access.
Has anyone any idea?