Partial Packet lost after large transfer | Cypress Semiconductor
Partial Packet lost after large transfer
I'm using the CY68013A as a USB bridge to an FPGA. Right now, OUT packets are working well. When the FPGA sends IN packets, however, sometimes the last few bytes which would be a short packet are not sent. This only seems to happen with larger buffers - 5000 bytes is fine, 1MB is fine, 2MB is not, 5MB is not, and 10MB is not (9999872 bytes works). PKTEND is being asserted correctly (verified by logic analyzer) and FIFO_ADR is stable.
I'm using BeginDataXfer/WaitForXfer/FinishXfer for this operation. Curiously enough, everything works fine until the last FinishXfer fails. I have no idea why - the UsbdStatus field doesn't return anything useful. FinishXfer does return instantly, though - there's no timeout or anything like that (unlike when I didn't assert pktend previously).
No handling of the buffers is done on the device itself, and AUTOIN is set. The rest of the data that is transferred is correct, it's just cut short. I am reasonably certain that all data is being sent, and that it is correct.
Can anyone shine some light on this?