Multi-Master I2C Capability | Cypress Semiconductor
Multi-Master I2C Capability
Are there any examples of I2C code for the 68013A that works in a multi-master environment. To be clear, I do not expect the 68013A to respond as a slave device.
From the TRM it looks like it should work, but there are a few questions.
What happens if there is a contention during the EEPROM boot load?
Does the I2C interface track the current state of the bus, i.e., if both the SCL and SDA lines are high and there has been a START without a STOP is the bus considered busy?
On page 190 of the TRM the BERR description says there is a deadlock condition. Assuming neither SCL nor SDA are stuck low will an externally synthesized STOP clear the bus?