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Multi-Master I2C Capability | Cypress Semiconductor

Multi-Master I2C Capability

Summary: 1 Reply, Latest post by aasi on 17 Jul 2012 02:49 AM PDT
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crhodin's picture
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Are there any examples of I2C code for the 68013A that works in a multi-master environment.  To be clear, I do not expect the 68013A to respond as a slave device.

From the TRM it looks like it should work, but there are a few questions. 

What happens if there is a contention during the EEPROM boot load?

Does the I2C interface track the current state of the bus, i.e., if both the SCL and SDA lines are high and there has been a START without a STOP is the bus considered busy?

On page 190 of the TRM the BERR description says there is a deadlock condition.  Assuming neither SCL nor SDA are stuck low will an externally synthesized STOP clear the bus?


Chris Rhodin

Aptina Imaging


aasi's picture
Cypress Employee
1166 posts

The I2C bus of FX2LP handles contention properly i.e. it will properly wait for the bus to be free before it drives anything so a externally synthesized STOP should clear the bus.

The trouble with the SCL and SDA being held low is that we've seen certain slaves which hold the SCL/SDA when there is miscommunication. If that happens you'll have to externally bring the I2C bus out of contention since FX2LP does not provide a way of clocking out the bus or other resolution mechanism.



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