How to perform Soft Reset that will be effectively equivalent to the Hard Reset. | Cypress Semiconductor
How to perform Soft Reset that will be effectively equivalent to the Hard Reset.
I'm using the EZ-USB for pushing data from my host PC to the device. (Bulk transfers, one way only)
I'm using external logic (Lattice FPGA) that looks only at the Fifo-full interrupt.
I am interfacing the Cypress EZ-USB FX2LP (Cy7C68013A) to a Lattice FPGA. The data is transferred to FPGA through the slave FIFO interface in AUTOIN mode (auto-commit with size of 512-byte) from PC.
Endpoint 2 is used, the fifo uses double buffering with packet size of 512 bytes. The external interface is set to 8 bits wide.
No data handling is performed in the FW code. (TD_Poll is empty)
Although I always validate that the overall data length sent from the Host is a multiple of 512 bytes, I guess that under rare conditions an error occurs and a different number of bytes is sent.
This rare condition causes my whole USB channel to come to a stall (I receive Timeouts in my WDU_TransferBulk call) in such a way that only a Hard Reset performed to the chip (pin #99) can resolve.
I am not concerned so much about data being lost in the specific corrupted transfer itself, but more in the ways to recover the channel for further transfers.
A hard reset is not an option, since it requires a redesign of the board, and a hence large delays in delivery.
So I thought to look for some "Soft Reset" that will be equivalent.
I tried two options, in some variants: (but without success) I added code to the ISR_Ures() that performs:
1. Perform FIFORESET to all endpoints. (Copy & Paste from TD_Init)
2. Perform EZUSB_Discon()
Both options brought the chip to some "non responsive" condition. I take it as an option that it is something wrong in my implementation.
I will be more then happy to get your recommendations, since this is a top priority issue in our company, that prevents from tens of machines from being delivered....
---- Please find our original code attached ----