How to indicate the EPxFIFO BUF overflow and stop the transfer forever | Cypress Semiconductor
How to indicate the EPxFIFO BUF overflow and stop the transfer forever
Thank you for your attentation.
What I used is CY7C68013A chip, the data streams continuously into the CY7C68013A from the extern master logic and the extern master logic can NOT stopped.
So whenever the host is too busy to receive the data from UBS, the overflow will occur in the CY7C68013A. I shall configure the EP2FIFO FULL flag interrupt to indicate the overflow occurs and stop the transfer.
firstly, I try to do it: if the EP2FIFO FULL flag interrupt is actived, assert the STALL bit of EP2. But it failed to stop transfer because the host maybe to recover the STALL.
What Should I do if I would to stop the transfer and prevent the host from recover the transfer again?
Thank you again!