hardware interface of cmos camera sesnor - Cy7C68013A 56-pin | Cypress Semiconductor
hardware interface of cmos camera sesnor - Cy7C68013A 56-pin
I need to interface 8 bit cmos camera to USB HS 2.0 controller (Cy7C68013A 56-pin). The 16 line pin outs of the camera is mentioned (also attached).
Eight data lines (D0-D7)
Three control and synchronisation lines (PCLK,VSYNC,HSYNC)
Two I2C lines (SDA,SCL)
One LED control line
The cmos camera has a resolution of 640x480 and gives the frame rate of 8 fps.
The data from the data lines (D0-D7) comes in sync with the PCLK (pixel clock) at a rate of 320ns. The cmos image sensor has a clock of its own which controls the PCLK signal.
I am now looking into the hardware interface of the cmos camera sensor with the cypress microcontroller (CY7C68013A 56-pin) and these are my interpretations on the hardware connections.
The cmos camera data lines (D0-D7) needs to be connected to PB0 to PB7 as the slave FIFO interface mode.
The I2C iterface on CY7C68013A is used to configure the cmos camera registers.
Data is valid when VSYNC, HSYNC, PCLK all are high. Where can I interface the PCLK, VSYNC and HSYNC signals ?
Do they need to be interfaced to read/write strobes (SLRD/SLWR) or the interrupt lines (INT0/INT1) on the micro controller.