GPIF and Programmable Full Flag problem | Cypress Semiconductor
GPIF and Programmable Full Flag problem
I've problem with using PF Flag with GPIF FlowState.
- GPIF works as master
- endpoint EP6 IN, bulk, 2x1024B
- externally GPIF is connected to FPGA (8-bit, 48MHz from Cypress)
Settings in C51 code:
- configure GPIF to use PF flag from EP6 fifo: EP6GPIFFLGSEL = 0x00;
- setting treshold for PF Flag:
EP6FIFOPFH = 0xC1; // 0b11000011
// EP6 FIFO Programmable Level Flag - low byte of Treshold byte count
EP6FIFOPFL = 0xFF; // Treshold 0x1FE = 510 bytes
- triggering GPIF transfer for 1024B
GPIFTCB1 = 0x04; SYNCDELAY;
GPIFTCB0 = 0x00; SYNCDELAY;
GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6 FIFO
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
GPIF FIFO Read waveform (see screenshots):
- DecisionPoint use TCXpire (RDY.5 is enabled for that)
- I use FlowState in state2 to continously read data
- FlowState checks EMPTY0 Flag (line from FPGA is constant '0') and FIFOFlag (should be PF in my example)
Problem is, that GPIF transfer seen an Logic Analyzer doesn't response on FIFOFlag as I expected.
It's no matter what is the treshold for Programmable Flag (I try 1023, 1000, 512, 510).
FlowState should change states of CTL lines (RD and CS) to 'high' after specified by treshold no of byte transfered to EP6 FIFO, but I see that CS and RD lines are 'low' until TCXpire finishes GPIF transfer (1024 bytes in my example)
Why FlowState doesn't response on FIFOFlag ( Programmable Flag ) in FlowState?
Is this related to "passing through IDLE state"?
Have anybody used Programmable Flag in GPIF?
I'll be gratefull for help