You are here

fx2lp receives zeros from FPGA !!! | Cypress Semiconductor

fx2lp receives zeros from FPGA !!!

Summary: 1 Reply, Latest post by Madhu Sudhan on 03 Aug 2016 01:40 PM PDT
Verified Answers: 0
Last post
Log in to post new comments.
okhunayn_1630511's picture
3 posts

I have altera cyclon V Soc DE1 and cypress cy7c68013a usb board FX2LP.
My project is send streaming data (counter from 0000 to FFFF) from FPGA to FX2LP.
After I connect data pins,flags,control signals and clock between FPGA and FX2LP ,FX2LP receives zeros , but when I connect data pins of FX2LP to 3.3V pin , the FX2LP pins receives high( 1 ).

I am using stream IN VHDL code from AN61345 project in  , and I modified PLL, DDR and Pins assignment for CycloneV ( because AN61345  using Xilinx Spartan 6 FPGA) . 
 Can anyone help me to know where is the problem??


mady's picture
Cypress Employee
955 posts


Can you please use a scope and see if the data lines are all zeros? If so, please check your connection. Also verify the data sent from the FPGA


-Madhu Sudhan

Log in to post new comments.