FX2LP, none standard FIFO usage | Cypress Semiconductor
FX2LP, none standard FIFO usage
I have this use case that I'm writing data to IN EP in async FIFO slave mode. The sender is a STM32 that output data via DMA and toggle SLWR with a timer.
For standard use I should monitor FIFO_FULL and stop writing immediately if it is asserted.
However STM32 input capture has this problem that it has to go through a resync process such that by the time FIFO_FULL is detected the next SLWR has already been issued.
So I'm thinking, can I set FIFO buffer to 512x2, then monitor the FIFO_EMPTY flag. Once FIFO is empty, I start STM32 DMA and send exact 512 bytes, then wait for the next FIFO_EMPTY
I wonder if it works, any dangerous and any performance hit?