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FX2LP, none standard FIFO usage | Cypress Semiconductor

FX2LP, none standard FIFO usage

Summary: 1 Reply, Latest post by Krishna GSNS on 25 Apr 2016 02:12 AM PDT
Verified Answers: 0
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baoshi.zhu_1641656's picture
User
1 post

Hi,

I have this use case that I'm writing data to IN EP in async FIFO slave mode. The sender is a STM32 that output data via DMA and toggle SLWR with a timer.

For standard use I should monitor FIFO_FULL and stop writing immediately if it is asserted.

However STM32 input capture has this problem that it has to go through a resync process such that by the time FIFO_FULL is detected the next SLWR has already been issued.

So I'm thinking, can I set FIFO buffer to 512x2, then monitor the FIFO_EMPTY flag. Once FIFO is empty, I start STM32 DMA and send exact 512 bytes, then wait for the next FIFO_EMPTY

I wonder if it works, any dangerous and any performance hit?

 

Thanks

 

Baoshi

Krishna GSNS's picture
Cypress Employee
48 posts

Hi Baoshi,

Yes you can use 512X2 buffer. It is better to use EP2. You can check whether the buffer is empty or not using FIFO empty status register. Please refer the TRM ( Technical Reference Manual) for the appropriate register. I do not think you will not see any issues if you send the data by checking the FIFO_EMPTY.

Thanks,

Krishna.

 

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